Enhancing RISC-V Performance Analysis Infrastructure

The RISC-V performance analysis infrastructure is evolving to address key competitive gaps in visibility and optimization across the stack. This work is essential to support the growing complexity of RISC-V-based systems and to ensure developers can effectively trace, profile, and tune their workloads for maximum efficiency.

The talk, given by Beeman Strong and Atish Patra (Rivos Inc.), will focus on:

• ISA extensions in development to enhance performance analysis capabilities;
• the enabling software infrastructure that supports these new features;
• enhancements that reduce profiling overhead and enable fine-grained monitoring in critical code sections; and
• tooling that supports dynamic tracing, instruction-level metrics, and visualization of performance hotspots.